There are many steps and processes involved producing microelectronic components such as computer processing units (CPUs) and application specific integrated circuits (ASICs), which are widely used in computers, cell phones, and portable electronics. Making electronics smaller and smaller raises new challenges in manufacturing CPUs and ASICs. Physical properties of the materials in semiconductor devices that previously did not affect the manufacturability or performance have become a major deterrent.
Designing modern electrical circuits such as CPUs and ASICs with wire dimensions of 130 nm and below has become increasingly difficult due to shrinking distance rules (“wire pitch”) which cause capacitive coupling between proximate wires. Coupling describes an electromagnetic effect where a signal change in one wire (aggressor wire) can affect the signal in a proximate wire (victim wire). The aggressor wire can either cause the victim wire to change its static value for a certain time span, a so called “glitch”, or it can cause a signal change in the victim wire to either speed up or slow down. In any case this can cause a digital system to fail because wrong signal values may be propagated.
Several approaches are known for eliminating the capacitive coupling between aggressor wires and victim wires.
The simplest approach to reduce coupling problems known in the art involves proceeding with standard routing and then fixing the problems with a post process, either manually or automatically. The standard routing would be done after timing closure based on the so called Steiner routes. Afterwards, the designer would do coupling analysis. Based on the analysis to avoid coupling problems logic changes are made by inserting repeaters or resized drivers in victim nets (the data representation of a wire in the design tools chain) and victim wires and optionally aggressor wires are rerouted with extra space using an isolated wire type.
The drawbacks are that the logic changes require the design infrastructure to support the ability to modify cells on routed designs. In the worst case, there is no solution, because adding additional buffers to timing critical nets can add too much delay or large enough drivers may not exist. Adding extra space consumes a lot of wiring resources and can have the side effect of causing detours, opens, or unwirability. If the extra space were a soft requirement, perhaps no detours or opens would be generated. However, the original issues would not be solved, especially in congested regions where coupling issues are most likely to occur.
Another approach, for example, involves routing all nets with a recommended extra space. As in the approach described above, a post processing is still required.
An automated method for analyzing crosstalk between wires is disclosed in the U.S. Pat. No. 6,507,935 B1. For at least one potential victim wire of a plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. An alarm threshold for each potential victim wire is determined and is compared to a calculated height of a coupled noise on the victim wire to determine which wires of the design suffer enough crosstalk noise that they should be redesigned. A similar approach is disclosed in the U.S. Pat. No. 6,327,542 B1, which proposes a method for determining an aggressor coupling capacitance and the coupling voltage noise. Both disclosures, however, suggest analyzing the crosstalk between the wires of a net. A post processing of the net is necessary, if the crosstalk level is too high.
A method for avoiding crosstalk between wires is disclosed in the U.S. Pat. No. 6,510,545 B1. Reducing the crosstalk is accomplished by introducing VDD and VSS wires proximate to signal wires on the same metal layer which reduce the crosstalk by shielding the signal wires. Such shields are implemented on all the wires of the net. Shields are deleted in areas where they are considered to be unnecessary. Although an efficient method to avoid crosstalk is suggested, the method is expensive and can practically only be applied to a small number of nets.
It is therefore an object of the invention to provide an improved integrated circuit design which allows for reducing coupling between wires in electronic circuits in a cost efficient way, thus avoiding unnecessary post processing, and corresponding computer programs, computer program products and computer systems.
The objects of the invention are achieved by the features of the independent claims. The other claims and the description disclose advantageous embodiments of the invention.